Floating Point Multiplication in a
Thursday, May 1, 2014 at 11:00 a.m.
Abstract: For this project we looked at an application of pipelining specifically in a floating point multiplier. A computer will generally have a floating point unit, which is a separate processing unit on the chip to deal with floating point arithmetic. Because multiplication at the binary level is made up of successive additions, it makes sense in terms of hardware to program in a cycle or loop which will re-use the same registers at each stage of the multiplication operation. However it makes the most sense time-wise to implement a pipelined multiplier which will use different registers for different stages of the operation. We have built 2 different floating point multipliers, one that is non-pipelined and one that is pipelined. We used a program called Logicworks which is a tool for interactive circuit design. After building the 2 different circuits we were able to do a side by side comparison of the timing, and see a significant increase in throughput in the pipelined multiplier.